Badge Panel | CypherCon 2.0

### Overview At CypherCon 2.0, a panel of six electronic badge creators discussed the technical and logistical realities of the "#badgelife" culture. The discussion covered hardware design trade-offs, microcontroller choices, protocol implementations, firmware development challenges, and the intense effort required to build, hand-assemble, and debug custom interactive conference badges.

### Key Topics - **Power Management & Switches:** The panel addressed why many badges omit hardware power switches. Surface-mount technology (SMT) switches frequently tear off or lift PCB pads when bumped. Some creators rely on standby sleep modes, software switching, or capacitive touch, while one team engineered a dual-button setup where a hardware switch bootstraps the regulator and software takes over to reduce standby current to 6 µA. - **Component Selection & Sourcing:** Component choice is primarily governed by cost, existing libraries, and availability. Sourcing surprises are common; one team experienced electrical noise issues with IrDA transceiver batches, while another had to hand-solder thousands of LEDs after lead-free reflow oven temperatures cracked APA102 LED packages. Sourcing parts early from overseas brokers before locking board layouts is critical. - **LED Protocols & Drivers:** The panelists debated addressable LED protocols. APA102 LEDs were praised for their separate hardware SPI clock line, enabling high data transfer rates and asynchronous transmission via DMA without bit-banging. In contrast, WS2812B LEDs require tight, strict timing, presenting challenges on 8-bit microcontrollers and specific MCU platforms like Nordic (due to 255-byte DMA packet limits), requiring circular buffers or assembly-level tuning. - **Assembly and Physical Constraints:** Panelists highlighted assembly constraints when building hundreds to thousands of boards. Constraints include avoiding QFNs, sticking to SOIC/QFP footprints, and choosing passive component sizes no smaller than 0603 to ensure manual placement with tweezers and stencils is feasible. - **Firmware Architecture & Memory Optimization:** Teams shared strategies for overcoming extreme memory limitations. One badge used two microcontrollers (a Microchip PIC and a Parallax Propeller). When Propeller code space ran out, strings were offloaded into the PIC's EEPROM, freeing memory for features like a custom text adventure, an operating system, and frequency generation for DTMF and phreaking modes. - **Interactivity and Easter Eggs:** The panel traced the evolution from simple static/blinking boards to interactive network nodes. Badges integrated peer-to-peer relaying, IrDA communication, telnet-style multi-hop chat, hidden Easter eggs (like silos and maze puzzles), and embedded games (such as Chip-8 emulators, Flappy Bird, and wireless multiplayer games).

### Technical Details - **Microcontrollers & Architectures:** Implementations discussed include Atmel XMega (hardware SPI and DMA), Microchip PIC (hardware IrDA SIR mode, assembly and C), Nordic MCUs, and the multi-core Parallax Propeller (programmed in Spin). - **Infrared & Communication Protocols:** IrDA SIR (Simple IR) mode acts as a glorified UART, pulsing high once every bit-time divided by 8 to sync and reject reflections. Other discussions noted repurposing badges for IR remote manipulation (TV-B-Gone style) and Bluetooth trolling. - **PCB Design:** One team highlighted designing multi-sided 3D cube badges with complex trace routing and zero vias on the outer faces.

### Takeaways Badge engineering requires balancing ambition with harsh physical and manufacturing realities. Builders must navigate component fragility, supply-chain variability, strict reflow profiles, and tight memory limits while writing regression-tested firmware under fixed conference deadlines.