Blacksmith: Compromising Target Row Refresh by Rowhammering in the Frequency Domain

### Overview In this talk, Patrick presents Blacksmith, a scalable Rowhammer testing tool and fuzzer operating in the frequency domain. As DRAM scaling has significantly reduced the activation threshold required to trigger bit flips—dropping from roughly 139,000 activations in DDR3 (2012) to around 10,000 activations in newer DDR4 devices (mid-2019)—DRAM manufacturers like Samsung, SK Hynix, and Micron deployed in-DRAM mitigations called Target Row Refresh (TRR). TRR mechanisms attempt to estimate frequently hammered rows and inject preventive refreshes before data loss occurs. However, Blacksmith demonstrates that existing TRR mitigations across major DDR4 and LPDDR4X devices are fundamentally flawed.

### Key Topics - **Target Row Refresh (TRR) Limitations**: TRR mitigations rely on frequent item count algorithms implemented under strict silicon area and timing constraints, often without formal security analysis. They typically comprise a sampler (which tracks activation frequencies) and an inhibitor (which issues preventive refreshes). - **Limitations of Uniform Hammering**: Prior attacks primarily used uniform n-sided patterns where all aggressors were accessed at identical frequencies, allowing sampler heuristics to track them easily. - **Frequency-Domain Rowhammering**: By systematically exploring non-uniform access patterns, the authors mapped critical attack parameters into frequency-domain properties: phase (timing/offset relative to refresh commands), amplitude (hammering intensity or peak access count), and frequency (hammering across multiple refresh intervals). - **Blacksmith Fuzzer**: A generic, extensible fuzzing framework that crafts complex patterns combining varied frequencies, phases, and amplitudes to systematically trigger bit flips.

### Technical Details - **Timing Window Constraints**: DRAM relies on JEDEC standard DDR timing, requiring cell retention for at least 64 ms with periodic refresh commands sent approximately every 7.8 µs on DDR4. In an interval between consecutive refreshes, an attacker can issue roughly 166 activations, summing to around 1.3 million activations across a full 64 ms refresh window. - **Parametric Observations**: - *Phase/Timing*: Testing on Samsung DIMM A10 showed bit flips only occurred when aggressor pairs were hammered immediately before a refresh command, suggesting sampler inactivity prior to refresh. - *Amplitude/Intensity*: Increasing hammering intensity boosted bit flips only up to a sweet spot; exceeding it caused flips to drop because the sampler detected the aggressor and triggered TRR. - *Frequency/Pattern Length*: Extending patterns over multiple refresh intervals (e.g., hammering heavily only every second interval) was necessary to induce flips on specific hardware, such as SK Hynix DIMM B2. - **Evaluation Results**: Evaluated against 40 test devices from Samsung, SK Hynix, and Micron, Blacksmith triggered bit flips on 100% (40/40) of the devices, outperforming Trespass (which triggered flips on 15/40). On a Samsung device (A17), Blacksmith produced roughly 138,000 bit flips. Additionally, all tested LPDDR4X devices were vulnerable. - **Exploitation**: Using established attack patterns, page table entry (PTE) exploits succeeded on 30 of 40 devices, yielding exploitable bit flips within three seconds to two hours and eight minutes. - **Generalization**: When approached by an unstudied vendor with an unanalyzed proprietary DDR4 device, Blacksmith discovered bit flips in less than four hours.

### Takeaways Current proprietary, obscure TRR implementations deployed by DRAM manufacturers fail to prevent Rowhammer bit flips under non-uniform, frequency-domain access patterns. The speaker concludes that hardware vendors must transition away from ad-hoc mitigations toward principled defenses with provable security guarantees, citing research such as ProTRR.