Bypassing KPTI Using the Speculative Behavior of the SWAPGS Instruction

## Overview

Andre Freire (Hypervisor-based memory introspection) and Dan Nemeth (Anti-exploit technology development), both from Bitdefender, presented SWAPGS—a new microarchitectural side-channel attack bypassing KPTI (Kernel Page Table Isolation), the primary software mitigation against Meltdown. SWAPGS exploits speculative execution of the x86 SWAPGS instruction to leak kernel memory despite KPTI protection. The attack demonstrates that even when classical Meltdown exploits are mitigated by KPTI's split page table architecture, alternative microarchitectural pathways—specifically speculative segmentation—enable memory disclosure. SWAPGS affects Intel 64-bit CPUs from Ivy Bridge onward (and AMD CPUs for a variant), Windows 7 and newer systems, while Linux kernels prove resistant due to architectural differences. Microsoft issued patches before public disclosure; Intel has not addressed this in silicon and does not plan to in the foreseeable future.

## Side-Channel Attack Primitives and Speculative Execution

**Cache Access Time Measurement**: Side-channel attacks infer victim behavior via careful measurements of CPU hardware state observable by attackers running on the same core. When attacker and victim code execute on the same hardware thread, the victim's memory operations modify cache content observable via timing measurements. Techniques include: (1) Flush+Reload—attacker flushes a test address from cache, executes victim code, then measures reload time (fast hit = victim accessed it, slow miss = victim did not); (2) Evict+Time—evict target address, execute victim, measure access time; (3) Prime+Probe—populate cache with known data, victim execution evicts some lines, attacker probes to detect which lines were touched.

**Speculative Execution Basics**: Modern CPUs use branch prediction to avoid pipeline stalls when conditional branch outcomes are unknown. The CPU speculatively executes predicted instructions before the branch resolves. If the prediction is correct, results commit to architectural state (visible to programmer). If incorrect, results are discarded but microarchitectural side effects (cache modifications, TLB updates) persist. Spectre exploits this: malicious speculative code accesses out-of-bounds memory, leaving cache traces that leak data even though the access violates bounds checking.

**Meltdown and KPTI Architecture**: Classical Meltdown exploits out-of-order memory loads in ring-3 (user mode) that transiently access kernel memory protected by page table permissions (user-supervisor bit). The CPU checks permissions only after the load commits, allowing transient leaks. KPTI mitigates by splitting page tables: user-mode page tables omit kernel virtual addresses entirely; kernel-mode page tables map both kernel and user space. When switching privilege levels, the page table register is reloaded. Without kernel VAs in user page tables, transient Meltdown-style kernel loads cannot obtain virtual addresses to translate, preventing memory leaks.

## SWAPGS: Exploiting Speculative Segmentation to Bypass KPTI

**Segmentation Mechanism**: x86 segmentation (a legacy protection mechanism predating paging) translates logical addresses (segment selector + offset) to linear addresses. Segment selectors index the Global Descriptor Table (GDT), retrieving segment descriptors containing base addresses and access rights. The CPU adds offset to the segment base to form a linear address, later translated via paging. Segmentation is implicit for most instructions (code segment CS for fetches, data segment DS for loads) but x86 allows segment overrides, permitting instructions to force use of non-default segments.

**Speculative Segmentation Vulnerability**: The SWAPGS instruction atomically exchanges GS and kernel GS segment registers, typically used for thread-local storage. When speculatively executed, SWAPGS can cause the CPU to use an incorrect segment register during address calculation. Two variants: (1) Type 1—SWAPGS fails to execute speculatively when it should, leaving kernel GS accessible to user code; (2) Type 2—SWAPGS executes speculatively even when it shouldn't, allowing user-specified segment overrides to calculate linear addresses with kernel segment bases. Type 2 enables attackers to bypass KPTI by speculatively forming kernel linear addresses via segment offset arithmetic, bypassing the page table permission checks.

**Attack Mechanics**: SWAPGS exploits allow an attacker to: (1) speculatively execute code accessing kernel memory using segment overrides, (2) leave cache traces of those accesses despite KPTI preventing page table translation of kernel VAs, (3) recover the traces via Flush+Reload or similar cache-based side channels. Because segmentation operates before paging in the address translation pipeline, segment-based linear address formation in speculative execution creates transient accesses that persist in cache even when the access would be rejected by page tables.

**Mitigation Status and Impact**: Microsoft released patches enabling SWAPGS instruction serialization and enhanced segmentation checks before disclosure. Intel microcode updates also available. However, Intel has not addressed the fundamental microarchitectural gap in silicon and does not plan to. Affected systems rely on software patches. Linux systems are resistant due to kernel design differences (different GS usage patterns, lack of equivalent KPTI split page table structure on all variants). The attack demonstrates that layered hardware protections (KPTI + paging + segmentation) create surprising interaction vulnerabilities when speculative execution is considered.