Custom Processing Unit: Tracing and Patching Intel Atom Microcode

Overview: Security researchers Pietro Borrello and Martin Schwarzl present the first software-based static and dynamic analysis framework designed to reverse engineer and patch Intel CPU microcode. Focusing on Intel Atom processors (Goldmont microarchitecture), the authors build upon hardware-level debugging access achieved via Positive Technologies' "red unlock" vulnerability. The presentation introduces custom tooling, including a Ghidra microcode decompiler and software interfaces to internal hardware buses, enabling live microcode tracing and modification.

Key Topics: - Intel x86 CPU microcode architecture, Microcode Sequencer, and match-and-patch logic - Utilizing Positive Technologies' Red Unlock vulnerability to access undocumented debugging states - Developing a dedicated Ghidra decompiler module for microcode Triads and sequence words - Interfacing with the Control Register (CR) bus and Logic/Array Dump and Test (LDAT) component - Software-based dynamic microcode tracing and reversing the microcode update algorithm (RC4)

Technical Details: While simple x86 instructions execute directly as single micro-operations, complex instructions such as CPUID require coordinated micro-operation streams handled by the CPU's Microcode Sequencer. Microcode is permanently stored in on-die ROM, structured into "Triads"—groups of three micro-operations accompanied by a fourth NOP and an overarching sequence word that controls execution flow, synchronization, and next-instruction pointers. To remediate post-silicon hardware defects, CPUs incorporate volatile microcode patch RAM alongside a "match-and-patch" hardware unit that monitors execution and redirects specified instruction addresses from ROM to patched micro-operations residing in RAM.

The authors capitalized on the "red unlock" research from Mark Ermolov and the Positive Technologies team, which exploited vulnerabilities in the Intel System Management Mode (SMM) engine to place the CPU into a manufacturing debug state, revealing decrypted microcode ROM and undocumented instructions. Because raw microcode disassembly is heavily tangled, dense, and shares code blocks across multiple functional areas, the researchers developed an automated Ghidra decompiler module. This tool parses microcode Triads, reconstructs control-flow graphs, and produces readable C pseudo-code, which exposed critical routines such as the RC4 decryption algorithm used during microcode update processing.

To manipulate microcode dynamically without hardware probes, the researchers analyzed the CPU's internal interconnects, specifically the Control Register (CR) bus. The CR bus manages internal communications, mapping Model-Specific Registers (MSRs), control/status registers, SMM configurations (Ring -2), and the LDAT (Logic/Array Dump and Test) post-silicon validation hardware. LDAT maintains direct read and write access to internal buffers, execution queues, TLBs, and the Microcode Sequencer. By chaining undocumented instructions discovered in red-unlocked states to interface with the CR bus, the researchers constructed software wrappers that route through LDAT to grant direct write access to the Microcode Sequencer's patch RAM, achieving arbitrary live microcode execution and tracing.

Key Takeaways: Proprietary CPU microcode can be effectively decompiled and analyzed using structured reverse engineering frameworks tailored for microcode semantics. Undocumented post-silicon diagnostic hardware like LDAT and internal control buses present significant attack surfaces if hardware debug locks are bypassed. Understanding microcode internals is critical for auditing CPU security, verifying hardware-level cryptographic routines, and evaluating low-level mitigations for transient execution vulnerabilities.

(AI summary — Gemini Flash)