Fault Attacks & Side Channels

### Overview This session focuses on physical attacks and countermeasures in cryptography, divided into two presentations. In the first talk, Guillaume Barbu presents joint work with Christophe Giraud on breaking recently proposed infective countermeasures for deterministic ECDSA using lattice-based fault attacks. In the second talk, Luke Beckwith presents hardware implementation work from PQSecure Technologies on post-quantum cryptography, specifically flexible, shared hardware acceleration and side-channel protection for CRYSTALS-Kyber and CRYSTALS-Dilithium.

### Key Topics - **Fault Attacks on Deterministic Signatures**: Fault injection techniques (e.g., laser, EM pulses, voltage/clock manipulation) and the distinction between detective countermeasures (execution redundancy with verification) and infective countermeasures (fault propagation without conditional aborts). - **Lattice-Based Fault Exploitation**: Combining additive fault injection models with lattice reduction algorithms (such as LLL and BKZ) to solve hidden number problem (HNP) instances. - **Post-Quantum Cryptography Hardware Acceleration**: Implementing NIST-standardized module learning with errors (MLWE) algorithms—CRYSTALS-Kyber and CRYSTALS-Dilithium—on FPGA. - **Side-Channel Protection via Masking**: Implementing domain-oriented masking (DOM) across Boolean and arithmetic domains to thwart power analysis attacks during sensitive operations like Kyber decapsulation.

### Technical Details - **Lattice Fault Attacks on ECDSA Countermeasures**: Barbu analyzes two infective countermeasures from CT-RSA 2022 and CHES 2022 designed for deterministic ECDSA. Using an additive fault model where an injected error satisfies an upper bound, faults are introduced during intermediate calculations (such as the point x-coordinate or blinding multiplications). Because random values are deterministically derived from the message, repeated injections on identical inputs allow constructing HNP instances. The attacker builds a lattice matrix incorporating known multiples and solves for short vectors via LLL/BKZ. Simulations across fault sizes from 64 to 250 bits showed a 100% secret key recovery rate using 10–15 faulty signatures for faults under 160 bits, and up to 245 bits, proving that infective countermeasures remain vulnerable even under random, large errors. - **PQSHIP Hardware Architecture**: Beckwith details a modular hardware accelerator targeting Artix-7 FPGAs and ASIC applications. The core architecture divides into memory, a shared SHA-3 module for hashing and sampling, a formatting unit, and a polynomial arithmetic unit. Performance tiers include lightweight (one butterfly unit), mid-range (two butterflies), and high-performance (a 2x2 butterfly unit processing two NTT layers simultaneously alongside parallel-in serial-out parsing). Shared resource modules between Kyber and Dilithium cut hardware resource usage by roughly 30% compared to separate instantiations, while on-the-fly polynomial sampling minimizes block RAM consumption. Compared to optimized Cortex-M4 software, the designs demonstrate speedups ranging from 20x to 300x across various operations. - **Side-Channel Masking Evaluation**: For Kyber decapsulation, domain-oriented masking splits sensitive data into two shares. Boolean masking protects hashing and sampling, while arithmetic masking protects polynomial NTT operations. Converting between domains via Boolean-to-arithmetic and arithmetic-to-Boolean converters introduces overhead, causing a ~2.5x increase in both circuit area and latency. Verification using Test Vector Leakage Assessment (TVLA) confirmed that the masked implementation exhibited no measurable side-channel leakage across fixed vs. random power traces.

### Takeaways - Infective countermeasures in asymmetric cryptography are exceptionally difficult to design soundly; heuristic masking and infection can still leave structural mathematical relations exploitable through lattice reduction. - Lattice-based fault attacks are potent tools because they do not require precise bit-flip or single-byte fault models and can succeed even with large, random additive errors. - For post-quantum MLWE algorithms, resource sharing and unified architectures provide substantial area savings across multiple security levels, making them suitable for hardware security modules and roots of trust.