RFNoC Accelerating The Spectrum with the FPGA

### Overcoming Host Processing Limits in Software-Defined Radio At 00:00, Neel Pandeya and Nate Temple from Ettus Research introduce RFNoC (RF Network-on-Chip), an open-source FPGA processing architecture for USRP software-defined radios at the Wireless Village. The speakers address the bandwidth limits of traditional host-based SDR architectures.

### The Host CPU Bottleneck in Wideband Signal Processing At 06:45, the presenters explain the computational bottleneck of streaming raw in-phase and quadrature (I/Q) samples over USB or Gigabit Ethernet to host CPUs. Processing multi-channel wideband spectrum strains host memory buses and CPU cache, frequently causing buffer overruns and dropped samples.

### Modular FPGA DSP Blocks and Direct Synthesis At 13:12, Pandeya and Temple detail the modular architecture of RFNoC. The framework allows developers to implement digital signal processing (DSP) algorithms—such as Fast Fourier Transforms (FFTs), digital down-converters (DDCs), and FIR filters—directly within FPGA logic using Vivado HLS or Verilog.

### High-Throughput Cellular Demodulation in Hardware At 20:01, the speakers demonstrate real-time hardware signal processing. By chaining FPGA blocks together, they demonstrate high-speed multichannel WCDMA and LTE spectrum analysis executed entirely on-device at full analog-to-digital converter rates without burdening host compute resources.

### Seamless GNU Radio Integration Concluding between 24:00 and 28:21, the presenters explain how RFNoC integrates with GNU Radio flowgraphs. Developers can control on-chip FPGA blocks using standard graphical blocks, combining FPGA acceleration with software prototyping flexibility.

(AI summary — Gemini Flash)