Plore - Side channel attacks on high security electronic safe locks

### The High-Security Standard of Electronic Safe Locks Commercial bank vaults, gun safes, and classified government storage containers increasingly rely on electronic safe locks rather than mechanical three-wheel dials. Certified under rigorous standards such as Underwriters Laboratories (UL) Type 1, these electronic locks are marketed as impervious to physical manipulation, lock picking, and brute-force guessing. At 00:49, security researcher Plore examines the physical and cryptographic integrity of widely deployed UL Type 1 safe locks (such as the Sargent and Greenleaf / S&G Titan series), demonstrating how fundamental hardware side-channel weaknesses allow attackers to extract 6-digit combinations without destructive drilling.

### Hardware Architecture of Spindle-Mounted Keypads The mechanical design of commercial electronic safes isolates the locking boltwork inside the heavy steel door. The only electrical connection between the exterior world and the interior lock housing is a multi-wire cable passing through a small central spindle hole: - **Exterior Interface:** The external keypad houses push buttons, status LEDs, and a battery compartment supplying 9V DC power to the safe. - **Interior Processing:** The internal lock case contains the motor/solenoid actuator, drive gears, and the primary microcontroller with non-volatile EEPROM storing master credentials. - **Attack Surface Constraints:** Because the external wires supply operating current to the internal microcontroller, any fluctuations in current consumption on the external power line directly reflect internal computational processes.

### Firmware Comparison Logic and Timing Discrepancies At 04:46, Plore deconstructs the firmware algorithm responsible for verifying the user's secret combination: - **Byte-by-Byte Verification:** When a user inputs a combination on the keypad, the microcontroller retrieves the true combination from EEPROM and enters a byte-by-byte comparison loop. - **Early-Exit Vulnerability:** The comparison logic exhibits a classic early-exit design: the moment an entered digit does not match the stored digit, the loop breaks immediately to avoid wasting CPU cycles. - **Timing Leakage:** At 08:15, Plore demonstrates that the duration of the comparison loop is directly proportional to how many leading digits are correct. A guess with zero correct digits fails immediately, while a guess with five correct digits takes significantly longer to reject.

### Exploiting Power Consumption and EEPROM Reads Beyond gross timing differences, the lock exhibits power analysis side channels during EEPROM retrieval. At 07:22, Plore illustrates the oscilloscope traces capturing current draw across the external power cable: - **Hamming Weight Power Spikes:** When the microcontroller reads stored PIN bytes from EEPROM into working RAM registers, internal transistor switching draws distinct electrical current profiles that correlate with the number of set bits (Hamming weight). - **Sub-Millisecond Resolution:** At 10:41, the researcher shows that monitoring current fluctuations between 1.0 and 2.5 milliseconds after keypad input reveals the exact instant internal comparisons fail, providing an unmistakable physical signature for individual correct digits. - **Lockout Avoidance:** Safe locks enforce a penalty lockout (freezing the lock for 10 minutes) after three incorrect attempts. However, because the timing leakage occurs during processing before the final reject counter increments, an automated tester can deduce individual digits sequentially without tripping lockout penalties.

### Proof of Concept Tooling and Defensive Hardening At 14:53, Plore demonstrates an automated hardware bypass device constructed from an Arduino/Teensy microcontroller and an analog amplifier plugged directly into the keypad's external battery terminals: - **Rapid Decryption:** The automated tool measures the power and timing profiles of candidate digits, successfully identifying the full 6-digit combination in less than fifteen minutes without physical damage. - **Defensive Firmware Best Practices:** At 18:08, Plore emphasizes the necessary mitigations for lock engineers: enforcing constant-time memory comparisons (`CRYPTO_memcmp`), removing early-exit branches, and adding algorithmic jitter or uniform dummy EEPROM reads to mask power draw and timing leakage across all authentication cycles.

(AI summary — Gemini 3.8 Flash)