The Big-endian RISC-V Linux Adventure

### Overview In this talk, Ben from Codethink presents an R&D project exploring big-endian support on the RISC-V architecture. While RISC-V is traditionally little-endian, recent revisions of the RISC-V privileged architecture specification introduced runtime control registers (CSR bits) allowing systems to switch data access endianness across machine (M), supervisor (S), and user (U) execution levels. Because no hardware or emulation existed with this feature implemented, Ben and a small team of Codethink engineers set out over a three-month research effort to build an end-to-end software stack—spanning QEMU emulation, OpenSBI firmware, the Linux kernel, and a Buildroot-based userland—running in big-endian mode.

### Key Topics - **RISC-V Endianness Architecture**: The privileged specification provides control bits in status CSRs (`mstatus` bit 37 for M mode, bit 36 for S mode, and a corresponding bit for U mode). Notably, endianness configuration applies strictly to data accesses (including integer and floating-point data); the instruction stream remains strictly little-endian, and the memory management unit (MMU) follows the endianness of S mode. - **QEMU & Hardware Emulation**: To bootstrap the environment without physical big-endian RISC-V silicon, the team modified QEMU (adding roughly 120 lines in `target/riscv`), implementing the CSR bits, internal big-endian data flags in translation blocks, memory operation flags, and page table adjustments. - **Firmware, Kernel, and Toolchain Integration**: GCC already supported `-mbig-endian`, but integration required patching OpenSBI (handling startup configuration and memory-mapped IO), modifying Linux kernel components, updating Buildroot, and configuring C libraries such as uClibc. - **Future Hardware and Ecosystem Collaboration**: The team initiated work porting big-endian support to CVA6 (an open-source RISC-V FPGA core) and announced collaboration with MIPS, who are developing the big-endian capable i8500 RISC-V core targeting networking workloads.

### Technical Details - **Instruction Stream Invariants**: Because instructions remain little-endian while data is big-endian, any software that introspects, modifies, or generates code faces subtle bugs. OpenSBI code hand-assembling instructions using `.word` directives caused the linker to endian-swap instruction bytes into invalid opcodes; fixing this required using the modern assembler `.insn` directive. In the Linux kernel, dynamic instruction modification routines—including static branches, trap handling (`BUG()` / `WARN()`), kprobes, uprobes, and BPF JIT—required endianness-aware adjustments. - **Atomic Operations and Locks**: Early full-system boots hung because Linux spinlocks rely heavily on sub-word atomic memory operations (load-modify-store), which failed until QEMU's atomic operations were properly updated for big-endian handling. - **Debugging the Unaligned Access Check**: An early boot crash occurred in the kernel's unaligned memory access self-test. The stack frame pointer (`s0`) pointed to valid memory, but an offset access faulted. Disassembly revealed that a hand-assembled `pause` instruction had been byte-swapped into a valid but unintended instruction that corrupted register offsets by adding 912 bytes to the stack pointer. - **Hypervisor Support**: Extending big-endian handling to the hypervisor extension involved virtualized status registers (`HSTATUS.VSBE` and `VSSTATUS`) and updating `kvmtool` to allow running guests with an endianness different from the host. - **Zbb Extension Comparison**: The presenter evaluated the RISC-V Zbb bit-manipulation extension (specifically byte-reversal instructions like `rev8`) against compiler bit-shifting routines on a VisionFive 2 board, noting up to a ~5x efficiency increase on 64-bit swaps.

### Takeaways Running a big-endian RISC-V Linux system is feasible with targeted modifications, primarily addressing IO accesses, atomic operations, and instruction stream introspection. The primary practical driver remains networking performance—eliminating byte-swapping overhead on network protocol headers—as well as easing migrations for legacy big-endian software stacks (such as PowerPC). With emerging hardware initiatives like MIPS's i8500 core and ongoing community patches, big-endian RISC-V is moving toward formal upstream support.